1. Field of the Invention
The present invention relates to a high voltage BICMOS device and a method for manufacturing the same.
2. Description of the Related Art
In general, in order to reduce a collector resistance of a bipolar transistor and to suppress a parasitic capacitance of a BICMOS transistor, a diffusion under field (referred to as ‘DUF’ hereinafter) region is formed. Typically, the DUF region may be characterized as a buried layer.
FIGS. 1 through 3 are cross-sectional views of a high voltage BICMOS device of a semiconductor device according to the related art for sequentially describing a method for manufacturing the BICMOS device.
First, as shown in FIG. 1, a pad oxide layer 12 is formed on a semiconductor substrate 10. Further, so as to expose the DUF region of the semiconductor substrate 10, a photoresist pattern 14 is formed in a predetermined region of the pad oxide layer 12.
Next, using the photoresist pattern 14 as a mask, a predetermined depth of the semiconductor substrate 10 and the pad oxide layer 12 are etched to define a formation region 15 for the DUF region.
Next, as shown in FIG. 2, ions are implanted in an entire surface of the semiconductor substrate 10 on which the formation region 15 of the DUF region is formed in order to implant the ions in the region 15. A diffusion process is performed to diffuse the implanted ions to form the DUF region 16. Next, the photoresist pattern 14 is removed.
Finally, as shown in FIG. 3, the pad oxide layer 12 is removed. A selective epitaxial growth (SEG) process is carried out on the resulting structure, including the DUF region 16, to form an epitaxial layer 18 on the DUF region 16 and the substrate 10. Next, a photoresist pattern (not shown) for forming a high voltage well region is formed on the epitaxial layer 18. After ions have been implanted in the epitaxial layer 18 using the photoresist pattern as a mask, a diffusion process is performed therein to form a high voltage well region 20 in contact with the DUF region 16.
However, in the related art, the DUF region 16 formed by the diffusion process after the ion implantation diffuses the DUF region 16 in a longitudinal direction and a transverse direction. That is, the DUF region 16 is diffused by a width or distance A (FIG. 2) from the original formation region 15, and is further diffused by a width or distance B (FIG. 3) during formation of the epitaxial layer 18 and the high voltage well region 20.
Accordingly, a distance between adjacent DUF regions 16 becomes narrower, thereby leading to possible deterioration of the reliability of the device.